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셀로코(주)는 MOSIS의 한국공식대리점으로
 MOSIS(M.P.W)의 모든 제품을
한국내에 독점으로 공급할 수 있습니다.
   
 
 

소량의 Prototype 칩을 경제적인 가격으로 제작(MPW)
Full-Custom, Standard Cell, Customer Tooling(Wafer)
소량에서 Midium(500 ~ 2000 dies, etc) 까지 제작 가능
Dedicated Run(COT :Customer Owned Tooling) 가능
  => Run Schedule에 상관없이 사용자 일정에 맞춰 언제라도 제작 가능
 Mixed Signal(Analog와 Digital)로 설계된 블록의 검증
SiGe 공정을 이용한 초고주파 회로 설계
 다양한 Standard Cell 제공(ARM, Virage Logic, Aragio)
1달에 한 번 Run Schedule로 빠른 진행 및 빠른 납기 보장

   
 

 

 

CMOS Analog, Digital
CMOS RF
Image IC
CCD 이용 Display Chips
MEMS Device
SiGe 공정 및 Device
High/Low Voltage, Low Power

   
 
 

 

기업체, 연구소, 대학교에서 저렴하고 빠르게 소량의 Chip 제작를 원하는 분.
연구 개발용으로 새로운 기능·성능의 회로, 저전력 회로, 고속 회로등을 설계·제작
  하고자 하는 분.
국내 주요 Customer
  - ETRI, KETI, KERI, KRISS, 삼성, LG, 서울대, KAIST, 연세대, 서강대, 인하대
    고려대, 한양대, 경희대, 포항공대, 광운대, 광주과기원,

   

 

MOSIS Fabrication Processes

IBM Fabrication Processes

IBM SiGe BiCMOS Processes
Feature Size Process Name

CMOS
Vdd[V]

SiGe Ft [GHz] | BVceo(1) [V] Description

High   Performance

High   Breakdown
0.13 µm 8HP

1.2 2.5
3.3

200 | 1.77    

57 | 3.55    

5th generation SiGe technology for advanced RADAR and mmWave applications.
8WL

1.2
2.5
3.3

103 | 2.4    

54 | 4.7    

Reduced performance, cost effective technology for wireless applications.
0.18 µm 7HP

1.8
2.5
3.3

120 | 2.0    

20 | 4.75    

4th generation SiGe technology best suited for wireless and high-speed switches.
7WL

1.8
2.5
3.3

60 | 3.3    

29 | 6.0    

Reduced performance, yet most cost effective SiGe technology offered.
0.25 µm 6HP/6DM

2.5
3.3

47 | 3.3    

27 | 5.7    

3rd generation SiGe technology.
6WL

2.5
3.3

60 | 3.2    

29 | 6.0    

A descendant of 7WL, it integrates 0.25 µm CMOS with the 7WL SiGe NPN.
0.35 µm 5HPE

3.3
5.0

43 | 3.3    

19 | 9.6    

2nd generation SiGe technology with 0.35 µm CMOS and 0.5 µm SiGe NPN's.
5PAe

3.3
5.0

35 | 5.5    

25 | 7.5    

Intended for power amplifier applications, this process features Through Wafer Vias.
0.50 µm 5HP

3.3

51 | 3.3    

27 | 5.5    

1st generation SiGe technology.
5AM

3.3  

51 | 3.3    

27 | 5.5    

Similar to 5HP, but adds a thick top metal.
5DM 3.3  

51 | 3.3    

27 | 5.5    

Similar to 5HP but adds two thick top metals for high-Q inductors.
5PA 3.3  

51 | 3.3    

24 | 7.0    

Similar to 5AM, this process adds higher voltage NPN's for power amplifier applications.
A process comparison including Ft and Fmax can be found at the IBM BiCMOS Key Technology Specifications page.

(1) BVceo is not a voltage limit for biasing unless the NPN is operating under a forced Ib condition. Vce greater than BVceo is allowed for other bias configurations, lower base impedance leading to higher voltage limits.

 

IBM CMOS and IBM RF CMOS Processes
Feature Size Process Name Voltage (V)
Core | I/O 		Description
45 nm 12SOI 1.0 | 0.9 This energy-saving SOI process is suitable for a broader range of consumer electronics, including digital TVs and high-end mobile applications.
65 nm 10SF 1.0 | 1.8, 2.5 Excellent for consumer electronics, wireless communications, and other applications requiring high performance or system-on-a-chip.
10LPe/RFe 1.2  |  2.5 Tailored for power-sensitive applications in wireless communications and consumer electronics.
90 nm 9SF 1.0  |  2.5 Ideal for leading-edge microprocessors, communications, and computer data processing applications.
9LP/RF 1.2  |  2.5 Use for low-cost, high performance wireless applications, as Bluetooth, WLAN, cellular handsets, mobile TV, WiMax, UWB and GPS.
130 nm 8RF-DM 1.2  |  2.5 Use for low-cost, high performance wireless applications as Bluetooth, WLAN, cellular handsets and GPS.
8RF-LM 1.2  |  2.5 Similar to 8RF-DM, but uses LM top metal.
180 nm 7SF 1.8  |  3.3 Use for high-performance graphics, communications, and data processing applications.
7RF 1.8  |  3.3 Ideally suited for RF and wireless applications, as Bluetooth, LANs, cellular phones and RF identification tags.
7RF SOI 1.8  |  3.3 Optimized for RF switch applications, integrate multiple analog functions into single-chip solutions for mobile devices.
250 nm 6RF 2.5  |  3.3 This RF CMOS process is adapted for high frequency applications with a variety of passives (as high Q inductors, MIM and MOS capacitors, and MOS varactors) for mixed-signal and RF applications.

2010 IBM Fabrication Schedule 보기


MOSIS IBM University Program

IBM University Program Min. Size

Price
IBM 180nm SiGe (7WL) 4mm2

아래 연락처로
별도 문의
IBM 130nm CMOS(8RF-DM)

4mm2
IBM 90nm CMOS(9RF/9LP)

4mm2
IBM 65nm CMOS(10RFe/10LPe)

4mm2
IBM 45nm CMOS(12SOI)

4mm2

2009 Q4 지원 예정

        * 상기 면적보다 크게 제작 가능 합니다.
        * 02-3433-0020 / mosis-korea@mosis.com

TSMC Fabrication Processes

Feature Size

Process

Description

65 nm   Standard logic, RPO
  Mixed-mode/RF, RPO, MiM
90 nm    Standard logic, RPO
  Mixed-mode/RF, RPO, MiM
0.13 µm  CL013G Standard logic, RPO
CR013G (CM013) Mixed-mode, RPO, MiM
CL013LP Low-power logic, RPO
CL013LV Low-voltage logic, RPO
0.18 µm  CL018 Standard logic, RPO
CR018 (CM018) Mixed-mode/RF, RPO, MiM
CL018LP Low-power logic, RPO
CL018LV Low-voltage logic, RPO
CL018HV High-voltage, RPO
0.25 µm  CL025 Standard logic, RPO
CR025 (CM025) Mixed-mode/RF, RPO, MiM
0.35 µm  CL035 Standard logic, 5.0 V ESD, RPO
CM035 Mixed-mode/RF, 5.0 V ESD, PiP, 2-poly
CL035HV1 High-voltage, RPO
1 This process uses epitaxial wafers.

These processes use non-epitaxial wafers. Epitaxial wafers are available at an additional cost.

2010 TSMC Fabrication Schedule 보기

On Semiconductor Fabrication Processes
(formerly AMIS)

Feature Size Metal Voltage Description
0.35 4
4
4

3.3
3.3
3.3, 2.5, 1.8, or 1.2

Mixed-Mode,  I3T80
Mixed-Mode,  I3T50
Mixed-Mode,  I3T25
0.50 3 5 Mixed-Mode,  C5
0.70 3
2		 5
5

Mixed-Mode,  I2T100
Mixed-Mode,  I2T30

 

 

austriamicrosystems Fabrication Processes

Feature Size Metal Voltage Description
0.18 6 1.8/3.3 CMOS C18
 
  1.8 V, 5 V, 20 V, and 50 V devices on a single chip HV-CMOS H18
0.35 4 3.3/5 CMOS, 2-poly,  C35B4C3
 
  3.3/5 CMOS-Opto, 2-poly,  C35B4O1
 
  3.3/5 CMOS, Thick Metal, MiM,  C35B4M3
 
  50 HV-CMOS, High resistive poly,  H35B4D3

See Compare AMS 0.35 µm CMOS Processes
0.35 4 2.5 SiGe BiCMOS, MiM capacitor, and high resistive poly,  S35D4
0.80 2 50 HV-CMOS, 3-poly, high resistance, vertical NPN,  CXZ

 


 

 

To be considered ontime for an MPW run, layout and paperwork are due to MOSIS by 1 PM PT (Pacific/California Time) on the date listed.

 

 
   
셀로코 홈페이지 오신걸 환영합니다!