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MyLogic Station

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Digital Circuit Editor, Logic Simulator
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Circuit design can be largely divided into two stages: front-end design and back-end design. MyLogic Station is a tool for front-end design, which includes circuit design (schematic capture), circuit verification (function simulation), and EDIF generation (EDIF netlist generation), etc. In particular, the schematic editor (SchEd) for circuit design allows users to easily design desired circuits by using various design libraries that have already been designed, and supports various functions to build design libraries. In addition, the simulator (MySim) for verifying designed circuits can easily analyze circuit verification results using various options, and it can facilitate circuit verification by linking with SchEd.
Finally, it supports EDIF generator (Logic2EDIF) for interface with other tools.

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Configure MyLogic Station™

  • SchEd_Analoog : Schematic / Symbol Editor

  • Logic2SPICE: Extracts Standard SPICE, HSPICE, PSPICE, CDL

  • MySPICE: Analog Circuit (SPICE) Simulator

  • MyPostProcessor : Graphical Simulation Analyzer

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  • SchEd: Schematic Editor: State Diagram Editor

  •  Supports on-line circuit check

  • Structural VHDL generation

  • Boolean Equations

  • Schematic generation from EDIF netlist

  • MState Diagram Editor

  • EDIF netlist generation

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  • MySim: Logic Simulator

  •  Logic level simulator

  • Supports typing commands

  • Waveform Analyzer

  • Easy to draw waveform for stimulus

  • Test bench generation for VHDL simulation

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  • Logic2EDIF: EDIF Netlist Generator

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  • SchGen (EDIF2Logic) : Schematic Generator

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