MyVHDL Station

VHDL Compiler & Simulator

MyVHDL Station supports IEEE std 1076-1987 VHDL language, which is the current standard VHDL, and can verify behavior and structure technologies using VHDL as well as mixed technologies, and IEEE std including record data type, file type, and dynamic ALLOCATION. 1076-1987 VHDL language is fully supported. In addition, by adopting a compiled code method that analyzes the design code designed by the user and creates a simulator that can effectively verify the design, it is compared to the existing version of the interpretive simulation method. Run faster simulations. MyVHDL provides an environment for performing verification through GUI as well as a command input method so that users can select a design verification environment.

Configure MyVHDL Station™

MyVHDL : VHDL Code Editor, Compiler, Simulator
WaveForm Editor: Automatic Test Bench Generator

MyVHDL : VHDL Code Editor, Compiler, Simulator
Supports both IEEE 1076-1987 and 1076-1993 VHDL standard
Supports Text I/O Library
File Read/Write
Textio.vhd, Std_logic_textio.vhd
Provides VHDL Wizard, syntax coloring, and other features to edit a VHDL file easily
User Friendly GUI and Various Wizards
Provides various kinds of debugging information for efficient debugging
Provides Smart Compile of the file base
Allows you to perform operations using commands
WaveForm Editor: Automatic Test Bench Generator
Automatic Test-Bench generation from waveform.